MIS semiconductor device having an LDD structure and a manufacturing method therefor

ABSTRACT

It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped impurity regions are formed. A coating mainly made of silicon is formed on the entire surface including the surface of the gate electrode. Side walls mainly made of silicon are formed on the side faces of the gate electrode by anisotropically or semi-anisotropically etching the thus-formed coating in an atmosphere of ClF 3 , for instance. In this etching step, since a selective etching ratio of the side walls to the gate insulating film is sufficiently large, etching of the gate insulating film is negligible. A source and a drain are then formed by doping an impurity at a high concentration using the gate electrode and the side walls as a mask.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a MIS(metal-insulator-semiconductor) semiconductor device such as a MOSfield-effect transistor and to a manufacturing method therefor. The MISsemiconductor device according to the present invention is used invarious semiconductor integrated circuits.

[0003] 2. Description of the Related Art

[0004] With the size reduction in design rules of MIS semiconductordevices, a strong electric field between the drain and the channel nowcauses a hot carrier injection phenomenon. Degradations incharacteristics due to the size reduction in design rules (i.e.,shortening of the channel) are generally called short channel effects.To suppress the short channel effects, as shown in FIG. 4, a MIS fieldeffect transistor having lightly doped impurity regions (lightly dopeddrain) 406 and 407 has been developed.

[0005] In this type of device, the LDDs 406 and 407 having an impurityconcentration lower than a source 404 and a drain 405 are providedbetween the source 404 and a channel forming region and between thedrain 405 and the channel forming region. Having an effect of reducingthe electric field, the LDDs 406 and 407 can suppress generation of hotcarriers.

[0006] Conventionally, the LDDs 406 and 407 shown in FIG. 4 are formedin the following manner. After a gate electrode 401 is formed, lightlydoped impurity regions are formed by doping. Then, side walls 402 areformed with an insulating material such as silicon oxide, and the sourceand drain 404 and 405 are formed by conducting doping in a self-alignedmanner using the side walls 402 as a mask.

[0007] However, since the gate electrode 401 does not extends over theLDDs 406 and 407, the further channel reduction has caused a phenomenonin which hot carriers are trapped in portions of a gate insulating film403 over the LDDs 406 and 407. The trapping of hot carriers,particularly hot electrons, reverses the conductivity type of the LDDs406 and 407, to unavoidably causes such short channel effects as athreshold voltage variation, an increase of the subthresholdcoefficient, and a reduction of the punch-through breakdown voltage.

[0008] To solve the above problem, the overlap LDD (GOLD) structure hasbeen proposed in which the LDDs are also covered with the gateelectrode. By employing this structure, there can be avoided theabove-mentioned degradation in characteristics which would otherwise becaused by hot carriers trapped in the gate electrode over the LDDs.

[0009] As the MIS field-effect transistors having the GOLD structure,there was reported an IT-LDD structure (T. Y. Huang: IEDM Tech. Digest742 (1986)). The IT-LDD structure means a LDD structure having aninverse-T gate electrode. FIGS. 3A to 3E schematically show amanufacturing method of such a transistor.

[0010] After a field insulating film 302 and a gate insulating film 303are formed on a semiconductor substrate 301, a conductive coating 304of, for instance, polycrystalline silicon is formed. (FIG. 3A)

[0011] A gate electrode 306 is then formed by etching the conductivecoating 304 to a proper extent. Care should be taken not to etch theconductive coating 304 completely; that is, only portions 305 indicatedby dashed lines should be etched to leave portions having a properthickness (100 to 1,000 Å) around the gate electrode 304, to therebyform a thin conductive coating 307. Therefore, this etching step is verydifficult.

[0012] LDDs 308 and 309 are formed by through-doping that is performedthrough the thin conductive coating 307 and the gate insulating film303. (FIG. 3B)

[0013] A coating 310 is then formed on the entire surface with such amaterial as silicon oxide. (FIG. 3C)

[0014] Subsequently, side walls 312 are formed by anisotropicallyetching the coating 310 in the same manner as in the case of producingthe conventional LDD structure. The thin conductive coating 307 is alsoetched in this etching step. A source 313 and a drain 314 are formed byconducting doping in a self-aligned manner using the side walls 312 as amask. (FIG. 3D)

[0015] Thereafter, an interlayer insulating film 315, a sourceelectrode/wiring 316, and a drain electrode/wiring 317 are formed tocomplete a MIS field-effect transistor. (FIG. 3E)

[0016] The resulting structure is called IT-LDD because the gateelectrode portion assumes an inverse-T as is apparent from the figures.In the ITLDD structure, in which the thinner portions of the gateelectrode exist over the LDDs, the carrier density in the LDD surfacescan be controlled to a certain extent from the gate electrode. As aresult, even if the impurity concentration of the LDDs is lowered, therecan be reduced the possibility of a reduction of the mutual conductancedue to a series resistance of the LDDs or variations of the devicecharacteristics due to hot carriers injected into the portions of theinsulating film over the LDDs.

[0017] These advantages are not specific to the IT-LDD structure, butcommon to all kinds of GOLD structures. Capable of lowering the impurityconcentration of the LDDs, the GOLD structure has a large effect ofreducing the electric field strength. Further, since the LDDs can bemade shallow, the GOLD structure can suppress the short channel effectsand the punch-through.

[0018] There are no effective GOLD structure manufacturing methods otherthan the method of the IT-LDD structure. Although the IT-LDD structurehave many advantages described above, it is very difficult to produceit. In particular, it is very difficult to control the etching of theconductive coating 307 (see FIG. 3B). If there occurs a variation of thethickness of the thin conductive coating 307 among substrates or withina substrate, the impurity concentration of the source and drain varies,resulting in variations of the transistor characteristics.

SUMMARY OF THE INVENTION

[0019] The present invention has been made in view of the above problemsin the art, and has an object of presenting a GOLD structure which canbe produced more easily.

[0020] According to the present invention, a manufacturing method of aMIS semiconductor device comprises the steps of:

[0021] (1) forming a gate insulating film on a surface of asemiconductor;

[0022] (2) forming a gate electrode central portion;

[0023] (3) forming a lightly doped impurity region (LDD) in thesemiconductor in a self-aligned manner using the gate electrode centralportion as a mask;

[0024] (4) forming a conductive coating mainly made of silicon;

[0025] (5) forming a side wall spacer on a side face of the gateelectrode central portion by anisotropically or semi-anisotropicallyetching the conductive coating in an atmosphere including a halogenfluoride; and

[0026] (6) forming a source or a drain in a self-aligned manner usingthe side wall as a mask.

[0027] The MIS semiconductor device produced by the above method ischaracterized by:

[0028] the gate electrode central portion formed on the gate insulatingfilm;

[0029] the gate electrode side portion mainly made of silicon and formedin close contact with the side face of the gate electrode centralportion; and

[0030] the LDD formed in the semiconductor under the gate electrode sideportion between the drain (or source) and the channel forming region.

[0031] The MIS semiconductor device is further characterized in that asingle insulating film mainly made of silicon oxide is formed on thedrain, source, channel forming region, and LDD.

[0032] In the semiconductor device manufacturing method according to thepresent invention, the side wall is formed with a conductive materialmainly made of silicon (i.e., formed with silicon having purity of morethan 95%). That is, a GOLD structure is obtained by making the side walla part of the gate electrode. To obtain such a structure, after aconductive coating mainly made of silicon is so formed as to cover aportion to become the gate electrode central portion, anisotropic orsemi-anisotropic etching is performed in an atmosphere including ahalogen fluoride. A halogen fluoride is represented by a chemicalformula XF_(n) where X is halogen excluding fluorine and n is aninteger. For example, ClF, ClF₃, BrF, BrF₃, IF and IF₃ may be used.

[0033] In the above description, the “gate electrode central portion” isa part of a gate electrode and corresponds to the gate electrode 401 ofthe conventional device shown in FIG. 4. Also, in the present invention,the portion (402 in FIG. 4) corresponding to the side wall of theconventional LDD structure is made of a conductive material havingsilicon as the main component. That portion is called the gate electrodeside portion as well as the side wall with a consideration that it isanother part of the gate electrode.

[0034] It is preferred that the gate electrode central portion be mainlymade of silicon, i.e., made of silicon having purity of more than 95%.

[0035] It is difficult to stop the etching for forming the side wall bymeans of the gate insulating film mainly made of silicon oxide, possiblyresulting in overetching of the substrate. This is due to the facts thatordinary dry -etching cannot provide a sufficiently large selectiveetching ratio of silicon to silicon oxide, and that the thickness of thegate insulating film is smaller (about 1/10) than that of the gateelectrode (i.e., side wall).

[0036] The investigations of the inventors of the present invention haverevealed that the above problems can be solved by etching with a halogenfluoride. This is based on the fact that while a halogen fluoride has astrong action of etching silicon, it has only a weak action of etchingsilicon oxide.

[0037] According to the present invention, in the etching for formingthe side wall, it is possible to make the selective etching ratio of theside wall to the gate insulating film sufficiently large. As a result,overetching of not only the semiconductor substrate but also the gateinsulating film can be avoided.

[0038] However, while it is possible to perform isotropic etching usinga halogen fluoride gas in a normal gas phase, it cannot realizeanisotropic or semi-anisotropic etching. After conducting investigationsunder various conditions, the inventors have found that the anisotropyof gas etching can be improved by additionally using plasma excitationin a weak RIE (reactive ion etching) mode. This is based on the featurethat plasma-damaged portion are likely etched by a halogen fluoride. Theanisotropy of etching can be improved by causing plasma ions orelectrodes to strike the substrate vertically. In a typical example, itwas possible to make the vertical etching rate 2 to 10 times faster thanthe horizontal one.

[0039] For the purpose of anisotropic etching, it is preferred that anatmosphere be mixed with a gas, such as an argon gas, which helpsgenerate plasma. It is further preferred to provide a mechanism capableof applying ions after accelerating those. However, it should be notedthat excessive plasma excitation causes reduction of the selectiveetching ratio of silicon to silicon oxide.

[0040] In the conventional dry etching, the function of plasma is togenerate an active species such as a fluoride ion. On the other hand, inthe etching of the present invention, plasma serves only to activate thesurface to be etched, i.e., facilitate its etching. The etching itselfis performed by a halogen fluoride. In other words, the halogen fluoridegas may not be necessarily converted to a plasma. Rather, it is onlynecessary to create a plasma which is sufficient to treat a surface sothat the surface states on an upper surface and a side surface differfrom each other.

[0041] The present invention is characterized in that anisotropicetching is performed by using a halogen fluoride. As for the details ofthe anisotropic etching, there may be used methods other than theabove-mentioned method of using plasma.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042]FIGS. 1A to 1E show a manufacturing method of a GOLD transistoraccording to a first embodiment of the present invention;

[0043]FIGS. 2A to 2E show a manufacturing method of a GOLD transistoraccording to a second embodiment of the present invention;

[0044]FIGS. 3A to 3E show a manufacturing method of an IT-LDD transistoraccording to a conventional method;

[0045]FIG. 4 shows a transistor having a conventional LDD structure; and

[0046]FIG. 5 schematically shows an etching apparatus used in the secondembodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] Embodiment 1

[0048]FIGS. 1A to 1E show a manufacturing method according to thisembodiment. First, a field insulating film 102 having a thickness of3,000 Å to 1 μm was formed on a silicon substrate 101 by a known LOCOSforming method. A silicon oxide film having a thickness of 100 to 500 Åas a gate insulating film 103 was then formed by thermal oxidation. Apolycrystalline silicon film having a thickness of 2,000 to 5,000 Åwhose conductivity was increased by doping of phosphorus was depositedby thermal CVD, and etched into a central portion 104 of a gateelectrode. Further, N-type, lightly doped impurity regions (hereinaftercalled LDDs) 105 and 106 were formed by implanting phosphorus ions in aself-aligned manner using the gate electrode central portion 104 as amask. It was preferable that the LDDs 105 and 106 have a phosphorusconcentration of 1×10¹⁶ to 1×10¹⁷ atoms/cm³ and a depth of 300 to 1,000Å. (Fig. 1A)

[0049] Subsequently, a polycrystalline silicon film 107 having athickness of 2,000 Å to 1 μm whose conductivity was increased by dopingof phosphorus was deposited by thermal CVD. (Fig. 1B)

[0050] Thereafter, anisotropic etching was performed with ClF₃ in thefollowing manner. The substrate was placed in an etching chamber (thesame as the one used for ordinary dry etching), a mixed gas of argon andClF₃ was introduced into the chamber, and RF discharge was effected.Flow rates of argon and ClF₃ were respectively set at 100 sccm and 50sccm, and the pressure was set at 0.1 Torr. The substrate wasself-biased at −50 to −200 V. The etching was almost stopped by the gateinsulating film 103, to exhibit almost no overetching.

[0051] As a result, a portion 108 of the polycrystalline silicon film107 indicated by a dashed line was etched to form gate electrode sideportions 109, i.e., what is called side walls, on the side faces of thegate electrode central portion 104. Under the conditions of thisembodiment, semi-anisotropic etching was effected in which the verticaletching rate was about two times of the horizontal one. Therefore, thegate electrode side portions 109 were somewhat narrower than in the caseof the complete anisotropic etching. (FIG. 1C)

[0052] Subsequently, a source 110 and a drain 111 were formed byconducting doping (implantation of arsenic ions) in a self-alignedmanner using the gate electrode central portion 104 and the sideportions 109 as a mask. The arsenic concentration was set at 1×10¹⁹ to5×10²⁰ atoms/cm³. The. LDDs 105 and 106 and the source and drain 110 and111 were then re-crystallized by thermal annealing. (FIG. 1D)

[0053] Thereafter, a silicon oxide film 112 having a thickness of 3,000Å to 1 μm as an interlayer insulating film was deposited by thermal CVD.After contact holes were formed in the silicon oxide film 112, a sourceelectrode 113 and a drain electrode 114 were formed. Thus, a GOLDtransistor was formed. (FIG. 1E)

[0054] Embodiment 2

[0055]FIGS. 2A to 2E show a manufacturing method according to thisembodiment. First, a field insulating film 202 having a thickness of3,000 Å to 1 μm was formed on a silicon substrate 201, and a siliconoxide film having a thickness of 100 to 500 Å as a gate insulating film203 was formed thereon by thermal oxidation. A central portion 204 of agate electrode was formed by using a polycrystalline silicon film havinga thickness of 2,000 to 5,000 Å whose conductivity was increased bydoping of phosphorus. Further, N-type LDDs 205 and 206 were formed byimplanting phosphorus ions in a self-aligned manner using the gateelectrode central portion 104 as a mask. (FIG. 2A)

[0056] Subsequently, a polycrystalline silicon film 207 having athickness of 2,000 Å to 1 μm whose conductivity was increased by dopingof phosphorus was deposited by thermal CVD. (FIG. 2B)

[0057] Thereafter, anisotropic etching was performed with ClF₃ in thefollowing manner.

[0058] An etching apparatus having a structure shown in FIG. 5 was used.A substrate 505 in the state of FIG. 2B was placed on a cathode 504 of achamber 501. An argon gas was introduced into the chamber 501, andplasma 508 was generated between an anode 502 and a grid 503 by means ofa RF power supply 507. On the other hand, a voltage difference betweenthe cathode 504 and the grid 503 was kept at such a value as to make thepotential of the anode 502 negative (−100 to−1,000 V). As a result,argon ions were accelerated toward the cathode 504 through the grid 503,and struck the substrate 505 approximately vertically.

[0059] On the other hand, a ClF₃ gas was jetted toward the cathode 504from shower-like gas inlets 506 that were disposed between the grid 507and the cathode 504. As a result, ion-damaged portions of the substrate505 were selectively etched, so that the anisotropy of the etching wasincreased to 10:1 in this embodiment.

[0060] In the above manner, a portion 208 of the polycrystalline siliconfilm 207 indicated by a dashed line was etched to form gate electrodeside portions 209, i.e., what is called side walls, on the side faces ofthe gate electrode central portion 204. (FIG. 2C)

[0061] Subsequently, a source 210 and a drain 211 were formed byconducting doping (implantation of arsenic ions) in a self-alignedmanner using the gate electrode central portion 204 and the sideportions 209 as a mask. The LDDs 205 and 206 and the source and drain210 and 211 were then re-crystallized by thermal annealing. (FIG. 2D)

[0062] Thereafter, a silicon oxide film having a thickness of 3,000 Å to1 μm as an interlayer insulating film 212 was deposited. After contactholes were formed in the interlayer insulating film 212, a sourceelectrode 213 and a drain electrode 214 were formed. Thus, a GOLDtransistor was formed. (FIG. 2E)

[0063] Although in the above embodiments, plasma was used for theanisotropic etching with a halogen fluoride, it would be apparent thatin the invention other methods can provide similar effects as long asthey are anisotropic or semi-anisotropic etching. Further, although theabove embodiments are directed to the case of forming a transistorwithin a semiconductor substrate, it goes without saying that similareffects can be obtained even where the invention is applied to a TFTthat is formed on an insulating substrate. Thus, the present inventionis useful from the industrial point of view.

[0064] As described above, in the semiconductor device manufacturingmethod according to the present invention, the side walls constitute apart of the gate electrode by forming the side walls with a conductivematerial mainly made of silicon. Therefore, a GOLD structure can beobtained not in the form of the IT-LDD structure.

[0065] Because the side walls are formed by performing anisotropic orsemi-anisotropic etching in an atmosphere including a halogen fluoride,the selective etching ratio of the side wall material to the gateinsulating film material can be made sufficiently large. As a result,overetching of not only the semiconductor substrate but also the gateinsulating film can be avoided. Thus, capable of easily controlling theetching, the present invention is suitable for mass-production of GOLDtransistors.

[0066] Also, as a modification of the present invention, it is possibleto conduct a pretreatment before conducting the anisotropic etching witha halogen fluoride. That is, by directing a plasma of argon verticallyto the substrate face, the surface conditions on the upper surface andthe side surface can be differentiated from each other. After thispretreatment, it is possible to perform an anisotropic etching using ahalogen fluoride gas without energizing the gas.

What is claimed is:
 1. A method of manufacturing a semiconductor devicecomprising the steps of: forming a conductive film over a substrate;treating a surface of said conductive film with an argon ion generatedby plasma; and etching said conductive film by using halogen fluorideafter the treatment with the argon ion.
 2. A method according to claim 1wherein said halogen fluoride is selected from the group consisting ofClF, ClF₃, BrF, BrF₃, IF and IF₃.
 3. A method according to claim 1wherein said conductive film comprises polycrystalline silicon.
 4. Amethod according to claim 1 wherein said substrate is self-biased at −50to −200 V during the etching.
 5. A method of manufacturing asemiconductor device comprising the steps of: forming a conductive filmover a substrate; directing a plasma of argon in a directionperpendicular to said substrate to activate a surface of said conductivefilm; and etching said conductive film by using halogen fluoride afterthe activation of the surface of said conductive film.
 6. A methodaccording to claim 5 wherein said halogen fluoride is selected from thegroup consisting of ClF, ClF₃, BrF, BrF₃, IF and IF₃.
 7. A methodaccording to claim 5 wherein said conductive film comprisespolycrystalline silicon.
 8. A method according to claim 5 wherein saidsubstrate is self-biased at −50 to −200 V during the etching.
 9. Amethod of manufacturing a semiconductor device comprising the steps of:forming a conductive film over a semiconductor film; treating a surfaceof said conductive film with an argon ion generated by plasma; etching apart of said conductive film using halogen fluoride after the treatmentwith the argon ion; and introducing an impurity ion into saidsemiconductor film by using the partially etched conductive film as amask.
 10. A method according to claim 9 wherein said halogen fluoride isselected from the group consisting of ClF, ClF₃, BrF, BrF₃, IF and IF₃.11. A method according to claim 9 wherein said conductive film comprisespolycrystalline silicon.
 12. A method of manufacturing a semiconductordevice comprising the steps of: forming a gate electrode over asemiconductor substrate; forming a conductive film over said gateelectrode; treating a surface of said conductive film with an argon iongenerated by plasma; and etching said conductive film using halogenfluoride after the treatment with the argon ion.
 13. A method accordingto claim 12 wherein said halogen fluoride is selected from the groupconsisting of ClF, ClF₃, BrF, BrF₃, IF and IF₃.
 14. A method accordingto claim 12 wherein said semiconductor substrate is self-biased at −50to −200 V during the etching.
 15. A method according to claim 12 whereinsaid conductive film comprises polycrystalline silicon.
 16. A method formanufacturing a semiconductor device comprising the steps of: forming agate electrode adjacent to a semiconductor substrate; forming aconductive film over said gate electrode; directing a plasma of argon ina direction perpendicular to said semiconductor substrate to activate asurface of said conductive film; and etching said conductive film byusing halogen fluoride after the activation of the surface of saidconductive film.
 17. A method according to claim 16 wherein said halogenfluoride is selected from the group consisting of ClF, ClF₃, BrF, BrF₃,IF and IF₃.
 18. A method according to claim 16 wherein saidsemiconductor substrate is self-biased at −50 to −200 V during theetching.
 19. A method according to claim 16 wherein said conductive filmcomprises polycrystalline silicon.
 20. A method of manufacturing asemiconductor device comprising the steps of: forming a gate electrodeover a semiconductor substrate; forming a conductive film over said gateelectrode; treating a surface of said conductive film with an argon iongenerated by plasma; etching a part of said conductive film usinghalogen fluoride after the treatment with the argon ion; and introducingan impurity ion into said semiconductor substrate by using the partiallyetched conductive film and said gate electrode as a mask.
 21. A methodaccording to claim 20 wherein said halogen fluoride is selected from thegroup consisting of ClF, ClF₃, BrF, BrF₃, IF and IF₃.
 22. A methodaccording to claim 20 wherein said semiconductor substrate isself-biased at −50 to −200 V during the etching.
 23. A method accordingto claim 20 wherein said conductive film comprises polycrystallinesilicon.